circuit note cn- 0259 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more i nformation and/or support , visit www.analog.com/cn0259 . devices connected /referenced ad 6657a quad if receiver , 200 msps sampling rate adl556 5 6.0 ghz ultrahigh dynamic range di fferential amplifier high performance 65 mhz bandwidth quad if receiver with anti a liasing filter and 184.32 msps sampling rate rev. b circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at roo m temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, co nsequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. evaluation and desig n support design and integration files schematics, layout files, bill of materials circuit function and benefits the circuit , shown in figure 1 , is a 65 mhz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11 - bit, 200 msps ad6657a q uad if receiver. the fourth - order butterwo rth anti aliasing filter is optimized based on the performance and interface requirements of the amplifier and if receiver. the total insertion loss due the filter network and other resistive components is only 2. 0 db. the overall circuit has a bandwidth of 65 mhz , with the low - pass filter having a 1 db bandwidth of 1 9 0 mhz and a 3 db bandwidth of 210 mhz. the pass - band flatness is 1 db . the circuit is optimized to process a 65 mhz bandwidth if signal centered at 140 mhz with a sampling rate of 184.32 msps . the snr and sfdr measured with a 1 4 0 mhz analog input across the 65 mhz band are 70.1 db fs and 80.9 dbc , respectively. 0.1f 0.1f 0.1f 0.1f ADL5565 g = 6db 2.2pf 40? 40? xfmr 1:1 z ect 1-1-13m input z = 50? z i = 200? internal input z ad6657a 11-bit 200msps if receiver 7.5pf 110nh 5? 5? 209? 50? 249? +3.3v +1.8v 1.875db loss 0.125db loss 2.0db loss 6db gain fs 1.75v p-p diff filter 72nh 110nh 72nh 0.1db loss analog input +4.9dbm at 10mhz overall gain = 3.9db vcm 110? r tadc 110? r tadc 0.1f r kb 15? r kb 15? r a 20? r a 20? r adc 2.4k? 1.5pf vip2 vin2 vip1 vin1 10443-001 figure 1. single channel of quad if receiver fron t e nd (simpli fied schematic: all connections and decoupling not shown) gains, losses, and signal levels measured values at 10 mhz
cn- 0259 circuit note rev. b | page 2 of 5 circuit description the circuit shown in figure 1 accepts a single - ended input and converts it to differe ntial using a wide bandwidth (3 ghz) m/a - com ect1 - 1 - 13m 1:1 transformer. the adl5 565 6.0 ghz differential amplifier has a differential input impedance of 200 ? when operating at a gain of 6 db , 100 ? when ope rating at a gain of 12 db, and 67 ? when operating at a gain of 15.5 db. the ADL5565 is an ideal driver for the ad 6657a , and the fully differential architecture through the low - pass filter and into the adc provides good high frequency common - mode rejection , as well as minimizes second - order distortion products. the ADL5565 provides a gain of 6 db, 12 db , or 15.5 db de pending on the input connection. in the circuit, a gain of 6 db was used to compensate for the insertion loss of the filter network and the transformer (approximately 2 .1 db), providing an overall signal gain of 4.0 db. the gain also helps minimize noise i mpacts from the amplifier. the ad6657a is a quad if receiver where each adc output is connected internally to a digital noise shaping requantizer (nsr) block. the integrated nsr circuitry allows for improved snr performance in a smaller frequency band within the nyquist bandwidth. the nsr block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sampl ing rate . for the data taken in this circuit note, the sampling rate was 184.32 msps , and the following nsr settings applied: ? nsr bandwidth = 3 6 % ? tuning word (tw) = 12 ? left band e dge = 11. 06 mhz ( i nput = 173 .26 mhz) ? center f requency = 44. 24 mhz ( i nput = 140 .08 mhz) ? right band e dge = 77.41 mhz ( i nput = 10 6.91 mhz) details of the operation of the nsr blocks can be found in the ad6657a data sheet. the anti aliasing filter is a fourth - order butterworth low - pass filter designed with a standard filter design program (agilent ads in this case) . a but terworth filter was chosen because of its flat response. a fourth - order filter yields a n ac noise bandwidth ratio of 1.0 3 . other filter design programs are available from nuhertz technologies or quite universal circuit simulator (qucs) simulation. to achie ve best performance, load the ADL5565 with a net differential load of at least 200 ? . the 20 ? series resistors isolate the filter capaci tance from the amplifier output and , when added with the downstream impedance , yield s a net load impedance of 2 4 9 ? . the 15 ? resistors in series with the adc inputs isolate internal switching transien ts from the filter and the amplifier. the 110 ? resistor s in parallel with the adc serve to reduce the input impedance of the adc for more predictable performance. the differential input impedance of the ad665 7a is approximately 2. 4 k? in parallel with 2.2 pf. the real and imaginary components are a function of input frequency for this type of switched capacitor input adc ; the analysis can be found in application no te an - 742. the fourth - order butterworth filter was designed with a source impedance of 50 ?, a load impedance of 2 0 9 ?, and a 3 db bandwidth of 1 9 0 mhz. the final circuit values for the filter are shown in figure 3 . the values generated from the filter program are shown in figure 2 . the values chosen for the filter passive components were the closest standard values to those generated by the program . the internal 2. 2 pf cap acitance of the adc was utilized as the final shunt capacitance in the filter design. a small amount of additional shunt capacitance (1.5 pf) was added into the final shunt capacitance at the adc inputs to help reduce kick back charge currents from the adc input sampling network and to optimize the filter performance. as seen with this design, obtaining the optimal performance can sometimes be an iterative process. the filter program design values were quite close to the final values, but due to some board parasitics , the final values of the filter were slightly different. figure 3 shows the final design values for the filter. 110nh 6.0pf 2.2pf ? ? 82nh 110nh ? 82nh 10443-002 figure 2 . filter program initial design for fourth - order differential butterwort h filter with z s = 50 ?, z l = 209 ?, f c = 1 9 0 mhz 72nh 7.5pf 3.7pf ? ? 110nh 72nh ? 110nh 10443-003 figure 3. final design values for fourth - order differential butterworth filter with z s = 50 ?, z l = 2 0 9 ?, f c = 1 9 0 mhz the measured performance of the system is summarized in table 1 , where the 3 db bandwidth is 210 mhz. the total insertion loss of the network is approximately 2 db. the bandwidth response of the final filter circuit is shown in figure 4 , and the snr, sfdr perfo rmance in figure 5 .
circuit note cn- 0259 rev. b | page 3 of 5 table 1 . measured performance of the circuit performance spec ifications at 1.75 v p - p fs final results cutoff frequency ( ? 1 db) 190 mhz cutoff frequency (?3 db) 210 mhz pass -b and flatness (10 mhz to 190 mhz) 1 db snrfs at 140 mhz 70.1 dbfs sfdr at 140 mhz 80.9 dbc h2/h3 at 140 mhz 97.7 dbc /80.9 dbc overall gain at 10 mhz 3.9db input drive at 10 mhz 4.9 dbm ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 10 100 1000 magnitude (dbfs) analog input frequenc y (mhz) 10443-004 figure 4 . pass- b and flatness performance vs. input frequency 65 70 75 80 85 107.5 1 12.5 1 17.5 122.5 127.5 132.5 137.5 142.5 147.5 152.5 157.5 162.5 167.5 172.5 snr (dbfs) and sfdr (dbc) analog input frequenc y (mhz) s fd r ( d b c) s nr ( d b f s ) 10443-005 figure 5 . snr/sfdr performance vs. inpu t frequency filter and interface design procedure in this section , a general approach to the design of t he amplifier/adc interface with filter is presented. t o achieve optimum performance (bandwidth, snr, sfdr, etc.), there are certain design constraints placed on the general circuit by the amplifier and the adc , such as : 1. the amplifier should see the correct dc load recommended by the data sheet for optimum performance. 2. the correct amount of series resistance must be used between the amplifier and the load presented by the filter. this is to prevent undesired peaking in the pass band. 3. the input to the adc sh ould be reduced by an external parallel resistor , and the correct series resistance should be used to isolate the adc from the filter. this series resistor also reduces peaking. this design approach will tend to minimize the insertion loss of the filter b y taking advantage of the relatively high input imp edance of most high speed adcs and the relatively low i mpedance of the driving source. details of the design procedure can be found in the cn - 0227 circuit note and the cn - 0238 circuit note . circuit optimization techniques and trade - o ffs the parameters in this interfa ce circuit are very interactive; therefore , it is almost impossible to optimize the circuit for all ke y specifications (bandwidth, bandwidth flatness, snr, sfdr, gain, etc.) . however, the peaking , which often occurs in the bandwidth response , can be minimized by varying r a and r kb . select t he series resistor on the adc inputs (r kb ) to minimize distortion caused by any residual charge injection from the internal sampling capacitor within the adc. increasing this resistor also tends to reduce bandwidth peaking. however, increasing r kb increases signal attenuation, and the amplifier must drive a larger sign al to fill the adc input range. another method for optimizing the pass - band flatness is to vary the filter shunt capacitor by a small amount. the adc input termination resistor ( 2 r tadc ) should normally be selected to make the net adc input impedance betwe en 200 ? and 400 ?. making it lower reduces the effect of the adc input capacitance and may stabilize the filter design, but increases the insertion loss of the circuit. increasing the value will also reduce peaking. balancing these trade - offs can be somewh at difficult. in this design, each parameter was given equal weight ; therefore , the values chosen are represent ative of the interface performance for all the design characteristics. in some designs , dif ferent values m ay be chosen to optimize sfdr, snr , or input drive level, depending on system requirements.
cn- 0259 circuit note rev. b | page 4 of 5 the sfdr performance in this design is determined by two factors : the amplif ier and the adc interface component values , as shown in figure 1 . the final sfdr performance num bers shown in table 1 and figure 5 were obtained after optimizing the filter design to account for the board parasitics and nonideal components used in the filter design . another trade - off that can be ma de in this particular design is the adc full - scale setting. the full - scale adc differential input voltage was set for 1.75 v p - p for the data obtained with this design, which optimizes sfdr . changing the full - scale input range to 2. 0 v p - p yields a small i mprovement in snr , but slightly degrades the sfdr performance . changing the full - scale input range in the opposite direction to 1.5 v p - p yields a small improvement in sfdr but slightly degrades the snr performance. note that the signal in this design is a c coupled with the 0.1 f capacitors to block the common - mode voltages between the amplifier, its termination resistors, and the adc inputs. r efer to the ad6657a data sheet for further details regarding common - mode voltages . passive component and pc board parasitic considerations the performance of this or any high speed circuit is highly dependent on proper pcb layout. this includes, but is not limited to, power supply bypassing, controlled impedance lines (w here required), component placement, signal routing, and power and ground planes. see the mt - 031 and mt - 101 tutorials for more detailed informatio n regarding pcb la yout for high speed adcs and amplifiers. use l ow parasitic surface - mount capacitors, inductors, and resistors for the passive components in the filter. the inductors chosen are from the coilcraft 0603cs series . the surface - mount capacitors used in the filt er are 5%, c0g, 0402- type for stability and accuracy. see the cn - 0 259 design support package ( www.analog.com/ cn0 259- designsupport ) for c omplete documentation on the system. c ommon variations for applications that require less bandwidth and lower power , the adl556 2 differential amplifier can be used. the adl556 2 has a bandwidth of 3.3 ghz. for even lower power and bandwidth , the ada4950 - 1 could also be used. th is device ha s a 1 ghz bandwidth and only uses 10 ma of current. circuit evaluation and t est t his circuit uses the e va l - cn0259 - hscz circuit board and the hsc - adc - e va l c z fpga - based data capture board. the two boards have mating high speed co nnectors, allowing for the quick setup and evaluation of the circuit's performance. the e va l - cn0259 - hscz board contains the circuit evaluated as described in this note, and the hsc - adc - e va l c z data capture board is used in conjunction with visual analog evaluation software, as well as the spi controller software to properly control the adc and capture the data. see the cn0259 design support package for the schematic, bom, and layout files for the e va l - cn0259 - hscz board. application note an - 835 contains complete details on how to set up the hardware and software to run the tests described in this circuit note. learn more cn - 0 259 design support package: http://www.analog.com/cn0259 - desig nsupport ug - 2 32 : evaluating the ad 6642/ad6657 analog to digital converters alex arrants, brad brannon and rob reeder, an - 835 application note: understanding high spee d adc testing and evaluation, analog devices. ar dizzoni, john. a practical guide to high - speed printed - circuit - board layout , analog dialogue 39 - 09, september 2005. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd , analog devices. mt - 101 tutorial, decoupling techniques , analog devices. agilent technologies, advanced design system . reeder, rob, frequency domain response of switched capacitor adcs , an - 742 application note, analog devices . reeder, rob , achieve cm convergence between amps and adcs , electronic design, july 2010. reeder, ro b, mine these high - speed adc layout nuggets for design gold , electronic design, september 15, 2011. rarely asked questions : considerations of high - speed converter pcb design, part 1: power and grou nd planes , design news, november 2010 . rarely asked questions: considerations of high - speed converter pcb design, part 2: using power and ground planes to your advantage , design news, february 20 11 rarely asked questions: considerations of high - speed converter pcb design, part 3: the e - pad low down , design news, june 2011 data sheets and evaluation boards cn - 0259 circuit evaluation board (eval - cn0259 - hscz) standard data capture platform (hsc - adc - evalcz) ad6657a data sheet ADL5565 data sheet ad6657a evaluation board (ad6657aebz)
circuit note cn- 0259 rev. b | page 5 of 5 revision history 8 /12 rev. a to rev. b changes to circuits from the lab descriptive header ................ 1 2/12 rev. 0 to rev. a c hanges to figure 1 ........................................................................... 1 changes to circuit description section and figure 3 .................. 2 changes to circuit evaluation and test section ........................... 4 1 /1 2 rev ison 0: initial version (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or other wise under any patents or other i ntellectual property by application or use of the circuits from the lab circuits. information furnished by analog devices is believed to be accurate and reliable. however, circuits from the lab circuits are supplied "as is" and without warranties of any ki nd, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of pa tents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do s o. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn10443 - 0 - 8/12(b)
|
